Field programmable gate array simulation and study on different multiplexer hardware for electronics and communication

Abstract

Multiplexing is the technique of transmitting two or more separate signals concurrently using a single communication channel. Multiplexing enables the augmentation of communication channels and consequently the volume of data that may be transmitted. Communication networks utilize diverse multiplexing techniques. An input multiplexer amalgamates various network signals into a singular composite signal before transmission over a shared medium. The composite signal is broken back into its component signals by a demultiplexer, when it reaches its destination, allowing further operations to utilize them separately. The design of the hardware chip depends on the configuration of the multiplexer and demultiplexer in the communication system. The work is presented as a study of the digital logic design and simulation of the different configurations of the multiplexer hardware. The performance evaluation is carried out on the different series of Xilinx field programmable gate array (FPGA) such as Spartan-6, Spartan-3E, Virtex-5, and Virtex-6 with logically checked in Xilinx ISE waveform simulator software. The current analysis of the design and simulation of different configurations of the multiplexer design helps the designers to estimate the chip performance. The novelty of the work lies in its scalable and programmable architecture fitted for specific communication systems that assess performance based on latency, frequency, and power consumption that can be further linked with communication protocols.